Logic functions

Boolean operations

Boolean variables or signals can only assume 2 states, which can be described with different mnemonics depending on the context

0	1
false	true
no	yes
off	on
low	high

In the following, the symbol X for "don't care" is also assumed, i.e. the value is irrelevant for the result. Flanks are indicated by the corresponding notation 0->1 or 1->0.

For comparison, the connection to the classic logic gate ICs of the 74 series is shown in many places (e.g. 74HC147). The function implemented in the Math module usually has even more options for the complex components than the designated model.

The simplest, elementary logic function is the inverting element "NOT":

	NOT A
A	(74HC04)
0	1
1	0

If two Boolean variables or signals are linked together, 2 elementary logic functions AND and OR are used:

		A AND B	A OR B	A XOR B
A	B	(74HC21)	(74HC32)	(74HC86)
0	0	0	0	0
0	1	0	1	1
1	0	0	1	1
1	1	1	1	0

The XOR element (Exclusive-OR) can be realized by a complex combination of AND, OR, and NOT and is listed here as a separate element to make the function easier to understand in the following.

$$XOR(A, B) = AND(OR(A,B), NOT(AND(A,B))$$

The combination with a NOT level results in

		A NAND B	A NOR B	A NXOR B
A	B	(74HC00)	(74HC02)	(74HC266)
0	0	1	1	1
0	1	1	0	0
1	0	1	0	0
1	1	0	0	1

The following logical operators and functions are used according to the data types, whereby the 64 bits of the numerical type <uint> (unsigned integer) are fed individually to the logic functions:

	<bool> A, B	<uint> A, B
NOT	!A	bNot(A)
AND	A && B	bAnd(A,B)
OR	A || B	bOr(A,B)
XOR	A ^^ B	bXOr(A,B)
NAND	!(A && B)	bNAnd(A,B)
NOR	!(A || B)	bNOr(A,B)
NXOR	!(A ^^ B)	bNXOr(A,B)

Bit-oriented functions

caution

These bit functions are not logical operators! They always work on the internal representation as <uint> and therefore convert all parameters to the <uint> type first. This can be seen, for example, in the bNot() function, which inverts all bits of the input value.

• bNot(false) => bNot(0x00) => 0xFFFFFFFFFFFFFFFFFF => logic: true.
• bNot(true) => bNot(0x01) => 0xFFFFFFFFFFFFFFFFFE => logic: true.

Even if the XOR operator ^^ is similar in result to != (unequal), the former enforces the data type <bool> for its operands, whereas != or == seeks the best possible representation for both data types and thus generally converts the Boolean operand into a numerical value 0 or 1 (<uint>, <int>, <dbl>) for the comparison when different data types are mixed.

Function	Description
bNot(x)	bit-oriented inversion of x (see also operator ~) For a logical NOT on a <bool> term, use the operator !.
bAnd(x1, ..., xN)	bitwise conjunction (AND) of all expressions x1, ..., xN
bNAnd(x1, ..., xN)	bitwise conjunction (AND) of all expressions x1, ..., xN with subsequent inversion
bOr(x1, ..., xN)	bitwise disjunction (OR) of all expressions x1, ..., xN
bNOr(x1, ..., xN)	bitwise disjunction (OR) of all expressions x1, ..., xN with subsequent inversion
bXor(x1, ..., xN)	exclusive bitwise disjunction (OR) of all expressions x1, ..., xN
bNXor(x1, ..., xN)	exclusive bitwise disjunction (OR) of all expressions x1, ..., xN with subsequent inversion
bShift(x,n)	bitwise shift (SHIFT) of x by n positions to the left, with negative n to the right
bCount(x)	Number of bits set in x
bTest(x,n)	Query whether the nth bit is set in x, n corresponds to the significance of the bit $2^n, n \in [0 ..63]$
bSet(x,n,v)	Set (v=true) or delete (v=false) the bit $2^n, n \in [0 ..63]$ in x

Logic elements

Edge detection "posedge", "negedge", "onchange"

For the edge detection elements, the input signal can be any numerical, scalar value of the type <bool>, <uint>,<int> or <dbl>.

Function	Description
posedge(x)	returns true for one nanosecond if the current value of the signal y is greater than its previous value
negedge(x)	returns true for one nanosecond if the current value of the signal y is smaller than its previous value
onchange(x)	returns true for one nanosecond if the current value of the signal y has changed compared to the previous value

note

Due to the extremely short duration of the signal of only 1 ns, such a signal is usually overlooked by the MQTT transmission. Only recordings in OSF files are therefore suitable for monitoring or visualization.

RS flip-flop "rsFF"

With true at the reset input, the output is set to false and with true at the set input, the output is set to true. reset has priority.

The inputs reset and set are interpreted as <bool>.

Q = rsFF(reset, set);
// Optional configuration
Qx = rsFF(..., { storage: <str>
               });

Property	Value	Description
storage	<str>	Name of a persistent memory for the internal state. This means that after a system restart, the output receives the last saved value. The content of this memory cannot be used anywhere else in smartCORE.

reset	set	output
0	0	Last state is held
0	1	1
1	X	0

JK flip-flop "jkFF"

With a rising edge at the clock input, the preparation inputs j and k decide how the output is changed (74HC73).

With true at the reset input, the output is set to false and with true at the set input, the output is set to true. reset has priority.

All inputs are interpreted as <bool>.

Q1 = jkFF(clock, j, k);
Q2 = jkFF(clock, j, k, reset);
Q3 = jkFF(clock, j, k, reset, set);
// Optional configuration for all variants
Qx = jkFF(..., { storage: <str>
               });

Property	Value	Description
storage	<str>	Name of a persistent memory for the internal state. This means that after a system restart, the output receives the last saved value. The content of this memory cannot be used anywhere else in smartCORE.

clock	j	k	reset	set	output
0	X	X	0	0	Last state is held
1	X	X	0	0	Last state is held
0->1	0	0	0	0	Last state is held
0->1	0	1	0	0	0
0->1	1	0	0	0	1
0->1	1	1	0	0	Output changes state
X	X	X	X	1	X
X	X	X	0	1	1

D-Flip-Flop "dFF"

With a rising edge at input clock, the value at input data is saved (74HC74).

With true at the reset input, the output is set to false and with true at the set input, the output is set to true. reset has priority.

This flip-flop can store all data types. With the exception of data, all inputs are interpreted as <bool>.

Q1 = dFF(clock, data);
Q2 = dFF(clock, data, reset);
Q3 = dFF(clock, data, reset, set);
// Optional configuration for all variants
Qx = dFF(..., { storage: <str>
              });

Property	Value	Description
storage	<str>	Name of a persistent memory for the internal state. This means that after a system restart, the output receives the last saved value. The content of this memory cannot be used anywhere else in smartCORE.

clock	data	reset	set	output
0	X	0	0	Last output value is held
1	X	0	0	Last output value is held
0->1	<var>	0	0	Output and storage of the value at data
X	X	1	X	The output is set to <false>
X	X	0	1	The output is set to <true>

D-Latch "dLatch"

With true at input hold the last value at input data is saved, otherwise the output immediately follows input data (74HC75) . This flip-flop can store all data types. The input hold is interpreted as <bool>.

Q = dLatch(hold, data);
// Optional configuration
Qx = dLatch(..., { storage: <str>
                 });

Property	Value	Description
storage	<str>	Name of a persistent memory for the internal state. This means that after a system restart, the output receives the last saved value. The content of this memory cannot be used anywhere else in smartCORE.

hold	data	output
0	<var>	Follows the value at data
1	X	Last output value is held

info

If hold and data change at the same time, the new data value is no longer used.

Multiplexer "select"

Multiplexer (74HC151), Via the index i a signal s0, s1, ... is selected and forwarded. If i is negative or greater than or equal to the number of inputs (n+1), false is output. The signals can represent any data type, the output also changes the data type accordingly.

y = select(i, s0, s1, ...sn);

i	s0	s1	...	sn	output
< 0	X	X	...	X	false
0	<var>	X	...	X	follows s0
1	X	<var>	...	X	follows s1
n	X	X	...	<var>	follows sn
> n	X	X	...	X	false

info

In the C programming language, this would correspond to the following statement:

switch(i)
{
case 0: return s0;
case 1: return s1;
// ...
case n: return sn;
default: return false;
}

tip

If the individual signals are already grouped as a vector, the Index syntax for vectors can be used more simply:

VSig = [s0, s1, ...sn]; // eventually result of calculation or buffering
yi = VSig[i];

However, care should then be taken to ensure that i remains in a valid value range [0 .. n].

Priority encoder "prioEnc"

Priority encoder (similar to 74HC147 or 74HC148), the index of the first active input is output in ascending order. Variants in functionality can be set using the optional configuration object. All inputs are interpreted as <bool>.

enc1 = prioEnc(e0, e1, ...);
// Optional configuration
encX = prioEnc(..., { none: <int>
                    , active: <bool>
                    , edge: <bool>
                    , map: [<int>]
                    , latch: <bool>
                    , startup: inf|<bool>
                    });

Property	Value	Description
none	<int>	If no input is active, this value is output (def.: -1)
active	<bool>	The level to be recognized as active (with edge: false) can be set here (def.: true).
edge	<bool>	With true, only positive (active: tue) or negative edges (active: false) are used for triggering.
map	[<int>]	Table for assigning output values for the control inputs e0, e1, ... e.g. [1, 10, 100, 1000]
latch	<bool>	With true the index of the last active input is held (radio button).
startup	inf/<bool>	Definition of a reference level for the inputs at software startup

In the following table, an input is active if the status defined by the properties active and edge applies. Otherwise inactive.

e0	e1	...	en	output
inactive	inactive	...	inactive	latch = false: -1 or value of the property none latch = true: the last activated value (radio button)
active	X	...	X	0 or the value defined with map[0]
inactive	active	...	X	1 or the value defined with map[1]
inactive	inactive	...	active	n or the value defined with map[n]

For the system start, you must define how the past of the inputs is handled and whether edges should be recognized immediately at startup. The startup property is used for this:

• inf: the first signal sample determines the value in the past before system start, so an edge is not triggered with the first sample.

• <bool>: The inputs are accepted with this signal value (true, false) in the past before system start. This may trigger an edge with the first sample of an input.

info

In the C programming language, this would correspond to the following statement (without edge, latch or startup):

if (e0 == active)
  return map.size() > 0 ? map[0] : 0;
else if (e1 == active)
  return map.size() > 0 ? map[1] : 1;
 // ...
else if (en == active)
  return map.size() > 0 ? map[n] : n;
else
  return none; // by default -1;