mvbdump
Configuration of smartIO MVB modules via USB
The description of this tool is in progress. Currently only the integrated help is printed.
Note: This software will no longer be supported in the future. The functionality will be integrated into the smiohp tool in future.
Options on the command line
usage: mvbdump <options>
recommended:
-i <inputBatchFile>
-c <c-sequence>
-s <inputDumpFile>
-o <dumpFile>
-f <format> (def = 0 [bin], 1, 2, ...)
-t <minutes> (def = 0: interactive mode)
-sl (synch to local time)
-sp <port> (synch to TIMEDATE48 in port)
-sw <offset> (synch to TIMEDATE48 at word offset)
optional:
-V print version
-u <usbDevice> (def = '', find by udev)
important: stty -F <usbDevice> raw -echo -echoe -echok
Sequence commands
entering interactive mode:
-q (terminate session)
-t <minutes> (end interactive mode)
-r (device txPreset)
-i <inputBatchFile>
-sl (synch to local time)
-sp <port> <offset> (synch to TIMEDATE48 in port / offset)
all other input will be send to the device.
FPGA control commands
- The configuration is carried out by the host via the send channel (Tx) of the serial USB interface, under which the smartIO is addressed.
- The FPGA has a minimalist API that is based on ASCII characters and is therefore easy to understand.
- There is no status feedback on the executed commands.
- As the control is typically carried out from a program code, there is essentially no integrated syntax check.
- The commands are interpreted and executed immediately upon transmission.
- Nevertheless, the FPGA uses the following typical syntax elements:
- all characters after // are ignored as comments until the end of the line (LF and/or CR)
- White space (0x09, 0x0A, 0x0D, 0x20) is generally ignored, exceptions are explicitly stated.
- Upper/lower case is ignored
The following functions can be operated via the API:
Direct commands
| Command | Description |
|---|---|
| R | RESET, stops test sequence and switches off input lines A and B |
| RRRR | Enforce high level RESET |
| L | Starts test sequence with loopback in the FPGA, line A and/or B must be activated beforehand |
| P | Starts test sequence with external loopback, line A and/or B must be activated beforehand |
| { | Stops test sequence and switches off input lines A and B, input of a new test sequence (see below) |
| ? | Returns the FPGA version number |
| @ | Return of the credits |
| # | Return of the hash key for the DBOA version |
| // | Comment, all characters up to the end of the line are ignored, always works |
As a switch
As a switch, consisting of a letter and immediately (without white space!) followed by the character '+' or '-' (defaults are "switched off")
| Command | Description |
|---|---|
| A+, A- | Reception on MVB line A, is switched off with RESET or program input/end |
| B+, B- | Reception on MVB line B, is switched on with RESET or program input/end |
| AB+, AB- | Switch reception on MVB lines A+B simultaneously, otherwise as above |
| C+, C- | Insert the received CRC into the data stream, e.g. commissioning diagnostics A status bit in the received MVB packet indicates whether CRCs are contained in the packet |
| E+, E- | Frames with error conditions are transmitted to the host for analysis |
| M+, M- | Switch on white list filter for real-time data in ports |
| W+, W- | Insert the Tx byte counter into the data frame, e.g. verification of the USB driver implementation |
| N+, N- | No-parity (or parity-don't-care) in CRC byte, not compliant with EN 91375-3-1§6.1.3: "The resulting 7-bit remainder shall be extended by an even parity bit." |
| X+, X- | Switch on white list filter for message communication |
| S+, S- | Activate ESD mode, termination after Log-0 and short EOF (MVB simulation only) |
As parameter command
As a parameter command, consist of a '=' letter combination (without white space!), followed by a +/- switch or numeric parameter values. The entries must always be made in hexadecimal notation with exactly the specified number of digits.
| Command | Parameter | Description | Example |
|---|---|---|---|
| =0 | Zero: delete all white list filters | =0 | |
| =D ## § | ## = Device - ID § = Message Mask | Device Flags: White-list filter for message communication, communication data is transmitted to the host for the specified device ID according to the mask. § is a 4-bit hex nibble with the following assignment: "transmitted if ..." bit0 (1): Single-cast with device ID as sender AND (*) bit1 (2): Broad-cast of device ID bit2 (4): Single-cast with device ID as receiver AND (*) bit3 (8): Single-cast with device ID (without direction) e.g. 'A' = bit1 + bit3, recording of all communication from/to this device | =D20 A |
| =P ###+, =P ###- | ### = Port - ID | Port Enable: White list filter for ports, with '+' the specified port is transmitted to the host | =P5B0+ |
| =T ### | ### = Slave Response Timeout/µs | Timeout: MVB works according to the standard with a timeout of 43 µs for the slave response. This time can be set with this command in the range 0...1023 µs. | =T02B |
| =X5 0# | # = Mapping | X5 header: Select pin mapping for pin header X5 #: Mapping index for C0 ... C1 - Pins | |
| =X7 # § | ## = Mapping | X7-Header: Select pin mapping for pin header X7 #: Mapping index for A0 ... A3 - pins §: Mapping index for B0 ... B3 - pins | |
| =R ### | ### = Table | Report: Output of a binary dump for the specified table 1: FIFO - read/write pointer, statemachine states 2: Tx-Prog-RAM 3: FIFO - channel A 4: FIFO - channel B 5: DSO Line A-RAM (deactivate scope beforehand!) 6: DSO Line B-RAM (deactivate scope beforehand!) | |
| =S 00# | # = Enable-Mask | Scope: Enable the internal DSO to record the input signals @ 24MHz (=> 16-bit / MVB-bit) The scope requires 22us until the triggers are armed to clear the RAM memory; 15 MVB bits including 2 MVB bits pre-trigger are recorded for each of the following 8 trigger events. The first data word contains the triggering triggers as well as further meta information and the current frame IDx. bit0: (1) Trigger with slave CRC error bit1: (2) Trigger with master CRC error bit2: (4) Trigger with symbol error bit3: (8) Trigger with frame start detection | =S 00C |
Simulation program
As a programming command for a test sequence, starting with {, followed by several program or data
program or data words separated by , and ending with }. To make it easier to create a test sequence, the FPGA can translate certain mnemonics as control commands and constant values.
Example:
{ .w 064 // Wait 100 µs
, .r 00A // Repeat 10 times ...
, .x 7 02 // (*) create frame with 2 data words with HDR, CRC and EOF
, $M // inserts the data word C715 as master header
, 0101 // Control command from master, read 16-bit port 257
, .w 0 04 // wait 4 us
, .x 7 02 // create frame with 2 data words with HDR, CRC and EOF
, $S // inserts the data word A8E3 as slave header
, 1234 // Simulated response byte from slave
, .w 010 // Wait 16 us
, .l 0 02 // Repeat from (*)
, .e 0 00 // Program end
}
The program memory contains 256 words that can be used for control commands and data. The programmed length is not checked in the FPGA or the driver library!
| Control word | Mnemonic | Parameter | Description | Example |
|---|---|---|---|---|
0000 | .e 0 00 | End: Program End | .e 0 00 | |
10## | .j 0 ## | ## = index of the target control word | Jump: Jump to the program word at position ##, counting starts at 0 | .j 0 02 |
2### | .r ### | ## = Initialization loop counter | Repeat: Allows a section of the program to be repeated n times n = [1 .. 4095] = [0x001 .. 0xFFF] Not cascadable ! | .r 00A.... .l 0 |
30## | .l 0 ## | ## = Index of the target control word | Loop: Decrement loop counter and jump to ## if greater than zero | .... .l 0 nn |
40## | .w ### | ### = time in µs | Wait: Wait for T = ### µs before executing the next command T = [1 .. 4095] = [0x001 .. 0xFFF] | .w 064 |
5§## | .f § ## | § = number of 1/2 fault bits## = start of the fault in 1/2 bits | Failure: Invert the simulated MVB output for § half bits after ## half bits. Control bit in .X command decides on line A/B | .f 2 1E |
6§## | .g § ## | § = number of words## = from data word | Generator: insert 16-bit PRBS values into the data stream instead of the specified data words, from word ## for § words for § = 0 16 data words are generated. | .g 8 01 |
7§## | .x § ## | § = control flags ## = number of words | eXchange: Transfers the following ## data words in the program as MVB data, whereby the following functions are switched with the control bits in the nibble-§: bit0 (1): first data word is MVB header bit1 (2): generate CRC bytes according to standard in the data stream bit2 (4): add EOF bits after the last data word to the frame the following ## words are sent as data words to the simulation output. (normal § := 7) | .x 7 02 , $M , 20B3 |
C§0# | .s § 0# | § = delay line# = time index | Skewing: Time shift between A/B line frames §: delay line B (0) or line A (1) 0:A first, B delayed 1: B: first, A: delayed #: time-index of delay, [0..7] 0: 0 .00 µs (perfect sync, never ever) 1: 0 .33 µs (1/2 bit time) 2: 1 .00 µs (3/2 bit times) 3: 7.65 µs 4: 7.99 µs (critical) 5: 8.30 µs 6: 9.67 µs 7: 10.34 µs Changing the time shift delays the execution of the following .X command until both bus lines are enabled again. | .S 0 04 |
D§$# | .d § $ # | § = Ctrl Line A$ = Ctrl Line B# = Debug out | Debug: §, $: Control Line A/B Simulation (normal §, $ := 3) bit0 (1): Enable line output bit1 (2): Enable line error bits bit2 (4): Start bit fault #: Control debug pins and options (2 lower bits are led out to X5) bit0 (1): Header X5:Pin X0, (select mapping 4, =X504) bit1 (2): Header X5:Pin X1, (select mapping 4, =X504) | .D 3 3 3 |
E§## | .+§ ## | § = command ## = parameter | Extended: reserved for extended command set | .+N ## |
E4## | .+w ## | ## = time grid in ms | Wait on ms-grid point, which is ## ms since last .+w command ahead | .+w 01 |
E... | tbd | |||
EF00 | .+N 00 | NoOperation | ||
F000 | .N 0 00 | NoOperation | ||
C715 | $M | As data word: MVB-MASTER header | ||
A8E3 | $S | As data word: MVB-SLAVE header | ||
7EC3 | $C | As data word: EN standard (6.1.3), example value for CRC calculation => CRC := 0xDD (with standard-compliant parity bit) |